1. Field of the Invention
The present invention is related to enforcing ordering rules between different transaction queues in an interconnect of a computer system that requires transaction ordering, such as the Peripheral Component Interconnect (PCI).
2. Description of the Related Art
Many industry standard and proprietary interconnects require transactions on the interconnect to be ordered according to certain rules to maintain memory consistency throughout the system or enable proper functioning of cache coherency protocols. Typically, all outstanding transaction ordering is accomplished using a transaction-ordering queue, while the individual transactions themselves are placed in multiple parallel queues. There must be a pointer in each entry of the ordering queue to point to the corresponding transaction in its own queue. The transactions must be removed in order from the transaction-ordering queue, but a transaction that lacks the resources to be executed is not allowed to block subsequent transactions and still has to be removed from the transaction-ordering queue. Its status must be updated (i.e., marked) in its own queue to show that it has no more dependencies on other queues. The current technique thus requires extra overhead and increases costs.